MOSFET Gate Resistor

Compare Miller-interval timing and constant-capacitance gate response with a shared resistor.

Formulas

Ig,on = Qgd / ton; |Ig,off| = Qgd / toff

Rext,on = (Vhigh − Vplateau) × ton / Qgd − Rsource − Rinternal

Rext,off = (Vplateau − Vlow) × toff / Qgd − Rsink − Rinternal

ton,pred = Qgd × (Rext + Rsource + Rinternal) / (Vhigh − Vplateau)

toff,pred = Qgd × (Rext + Rsink + Rinternal) / (Vplateau − Vlow)

RC only: t10–90 = ln(9) × Rtotal × Ceffective

RC only: Rext = t10–90 / [ln(9) × Ceffective] − Rdriver − Rinternal

Model & assumptions

N-channel enhancement MOSFET and resistive driver approximation; all gate voltages are source-relative. One external resistor is shared by both directions.

Miller charge and plateau depend on operating conditions. Timing estimates cover the drain-voltage transition interval, not total switching delay. Plateau current is not driver peak current.

The RC model uses an explicitly constant capacitance. In a linear control loop it estimates a local response, not loop stability or protection response.

Confirm timing and ringing on hardware. These models do not compute optimum damping or include gate-loop inductance. Unknown device data require explicit user assumptions.

Example with default inputs

Chosen common external resistor

27 Ω

External turn-on target

27 Ω

External turn-off target

18 Ω

Total turn-on target resistance

30 Ω

Total turn-off target resistance

20 Ω

Required plateau current · on

200 mA

Required plateau current · off magnitude

200 mA

Predicted VDS fall interval

100 ns

Predicted VDS rise interval

145 ns

Minimum modeled on interval

10 ns

Minimum modeled off interval

10 ns