Methodology & Formula Reference

Review formulas, assumptions, limitations, and numerical verification examples for all eight PowerLab calculators.
# PowerLab Tools — formula reference

Model version 1.0. Inputs are converted to volts, amperes, ohms and meters before calculation. Cable cross-section is in mm² paired explicitly with resistivity in Ω·mm²/m. Temperatures are in °C and temperature differences in °C (numerically equal to kelvin differences).

Calculation uses JavaScript IEEE-754 double precision without intermediate decimal rounding. Display formatting is separate. Required fields reject empty values, non-decimal strings, nonfinite values, incompatible signs and out-of-range inputs. Converter resolution is limited to integer 1–24 bits, with codes 0…2^N−1. Derived nonfinite outputs fail validation. Physical component limits require a separate datasheet review.

## 1. Voltage divider

R1 is the top resistor, R2 the bottom resistor, and RL the optional external load across R2.

```text
Vunloaded = Vin R2 / (R1 + R2)
Req = R2                         (no load)
Req = R2 / (1 + R2 / RL)         (with load)
Vloaded = Vin Req / (R1 + Req)
Itop = (Vin − Vloaded) / R1
P1 = (Vin − Vloaded)² / R1
P2 = Vloaded² / R2
PL = Vloaded² / RL               (zero when no load)
Ptotal = P1 + P2 + PL
error% = 100 (Vloaded − Vtarget) / |Vtarget|
```

The formulas follow Ohm's law, parallel resistance, and Kirchhoff's current law. `Ptotal = Vin × Itop` is an independent conservation check. Negative input voltages are supported; resistances must be positive. A zero target has no defined percentage error. A finite passive divider can reach only targets strictly between zero and the input, with matching polarity.

E24 suggestion: choose the nearest E24 bottom resistor, compute its loaded equivalent, solve `Rtop = Req(Vin/Vtarget−1)`, and round the top value to the nearest E24 nominal. Recompute and report the loaded suggested output/error. This is a nearby nominal pair, not a tolerance or power optimization.

Independent check: Vin=12 V, R1=1 kΩ, R2=2 kΩ, RL=2 kΩ → Vunloaded=8 V, Vloaded=6 V, Itop=6 mA, P1=36 mW, P2=18 mW, PL=18 mW, Ptotal=72 mW.

## 2. Shunt current sense

```text
Vshunt = Imax Rshunt
Vamp = Vshunt G
D = 2^N (ideal LSB) or 2^N−1 (endpoint)
code = clamp(floor(Vamp D / Vref), 0, 2^N−1)
current_per_count = Vref / (D G Rshunt)
Pshunt = Imax² Rshunt
minimum_rating = Pshunt (1 + extra_margin_percent / 100)
```

The ADC code uses an explicit floor-quantized ideal model. Exact device code transitions may differ. Input at or above the highest nominal code saturates. Output above Vref triggers an overrange warning; above 95% of Vref triggers a headroom review. This does not establish ADC absolute maximum or amplifier output/common-mode limits.

At 10 A, 0.047 Ω, gain 5, Vref=3.3 V, N=12, D=4096, extra margin=50%: Vshunt=0.47 V, Vamp=2.35 V, code=2916, resolution≈0.003428357712766 A/count, power=4.7 W, minimum rating=7.05 W.

Reference: [Texas Instruments, Optimizing Shunt Resistor Selection for Current Sensing (SBOA167)](https://www.ti.com/lit/an/sboa167/sboa167.pdf). Gain, input range, dissipation, and derating are separate design considerations.

## 3. Four-resistor differential op-amp

Topology: V1 → R1 → −IN; R2 from output to −IN. V2 → R3 → +IN; R4 from +IN to Vref.

```text
k = R2/R1
b = R4/(R3+R4)
Vplus = b V2 + (1−b) Vref
Vout = (1+k) Vplus − k V1
Ad = [(1+k)b + k] / 2
Acm = (1+k)b − k
ratio_mismatch% = 100 [(R4/R3)/(R2/R1) − 1]
```

`Ad` is the differential gain for V1=Vcm−Vdiff/2 and V2=Vcm+Vdiff/2 at fixed Vcm and reference. When R2/R1=R4/R3, Vout=k(V2−V1)+Vref and Acm=0. For mismatched ratios, the reference does not necessarily have unity gain.

Matched check: R1=R3=10 kΩ, R2=R4=100 kΩ, V1=1 V, V2=1.2 V, Vref=0.5 V → Ad=10, Vout=2.5 V, Acm=0. Mismatched check: R1=R3=R4=10 kΩ, R2=20 kΩ, V1=1 V, V2=2 V, Vref=0 → Vout=1 V, Ad=1.75, Acm=−0.5, mismatch=−50%.

The result remains an ideal linear output even when outside the entered rails; a warning explains saturation. Real common-mode and output swing limits depend on the actual op-amp and load.

Reference: [TI, Difference Amplifier (Subtractor) Circuit, SBOA274A](https://www.ti.com/lit/an/sboa274a/sboa274a.pdf). **Resistor labels differ:** TI's R3 is this app's feedback R2; TI's R2 is this app's positive-input R3. The circuit equations match after renaming.

## 4. OCP threshold

Zero-offset, positive-gain current sensing into an ideal comparator:

```text
Itrip = Vreference / (Rshunt G)
Vreference = Idesired Rshunt G
Grequired = Vreference / (Idesired Rshunt)
Rtop = Rbottom (Vsupply / Vreference − 1)
Vshunt_trip = Itrip Rshunt
Vamp_trip = Itrip Rshunt G
Pshunt_trip = Itrip² Rshunt
error% = 100 (Itrip − Idesired) / Idesired
```

Divider mode requires supply > desired reference and positive desired current. It reports ideal Rtop, then rounds to an E24 top resistor and uses that actual divider voltage for the reported actual trip current/error. The entered bottom resistor stays unchanged.

Hysteresis is explicitly a **heuristic**: reset current=0.95 Itrip, comparator voltage band=0.05 Vreference. This is not a feedback network synthesis. The actual design needs comparator output levels/polarity, reference impedance, feedback resistors, noise and timing.

Check: Rshunt=10 mΩ, G=20, Vreference=2 V → Itrip=10 A, Pshunt=1 W, suggested reset=9.5 A and band=0.1 V. For Vsupply=3.3 V, Rbottom=10 kΩ, target=10 A: ideal Rtop=6.5 kΩ, E24 Rtop=6.2 kΩ, actual trip≈10.185185 A.

Reference for hysteresis topology dependence: [TI, Non-inverting Comparator with Hysteresis](https://www.ti.com/tool/CIRCUIT060078). The 5% choice is an app design starting point, not a recommendation from that source.

## 5. MOSFET linear dissipation and thermal budget

```text
VDS = Vin − Vout
P = VDS Iload
theta_total = theta_JC + theta_CS + theta_SA
Tj = Tambient + P theta_total
Pmax_thermal = max(0, (Tj,max−Tambient)/theta_total)
theta_SA,max = (Tj,max−Tambient)/P − theta_JC − theta_CS
temperature_margin = Tj,max − Tj
power_margin = Pmax_thermal − P
```

Requires Vin≥Vout≥0, I≥0, each theta≥0 and positive total theta. At P=0 no heatsink limit is derived. Negative required heatsink resistance indicates an infeasible thermal budget. A temperature margin under 20°C triggers a heuristic review.

Check: Vin=24 V, Vout=12 V, I=3 A, Ta=25°C, Tmax=150°C, thetaJC=1, thetaCS=0.5, thetaSA=2°C/W → P=36 W, thetaTotal=3.5°C/W, Tj=151°C, margin=−1°C, Pmax≈35.714286 W, required thetaSA≤1.972222°C/W.

This is a steady-state single series heat path. It omits transient behavior, changing thermal resistance, parallel PCB paths, and local hot spots. Linear-mode loss is VDS×ID, not the fully-enhanced RDS(on) conduction formula.

**It does not verify MOSFET DC Safe Operating Area. Check the manufacturer SOA curve at the actual VDS, current, case temperature and operating duration.**

References: [Infineon, Linear Mode Operation and SOA](https://www.infineon.com/assets/row/public/documents/24/42/infineon-applicationnote-linear-mode-operation-safe-operation-diagram-mosfets-applicationnotes-en.pdf), [Infineon, Designing with Power MOSFETs](https://www.infineon.com/assets/row/public/documents/24/42/infineon-designing-with-power-mosfets-applicationnotes-en.pdf).

## 6. Cable voltage drop

Nominal resistivity at 20°C: annealed copper 0.017241 and electrical-conductor aluminum 0.028264 Ω·mm²/m. L is one-way physical length; n is the number of equal parallel conductors **per leg**.

```text
diameter_mm = 0.127 × 92^((36−AWG)/39)
area_mm2 = pi/4 × diameter_mm²
Leffective = L (one way) or 2L (round trip)
R = rho Leffective / (area n)
Vdrop = I R
Vload = Vsupply − Vdrop
Ploss = I² R
drop% = 100 Vdrop / Vsupply
efficiency% = 100 Vload / Vsupply
```

AWG mapping: 1/0=0, 2/0=−1, 3/0=−2, 4/0=−3. Equal current sharing is assumed. Drop above the supply produces a negative mathematical load voltage and a prominent infeasible-operating-point warning, rather than silently clamping results.

Default status bands are fixed design heuristics: ≤3% low drop, >3–5% review, >5% high drop. They are not ampacity limits or electrical-code compliance judgments. Temperature, contacts, AC skin effects and reactance are excluded.

Check: 12 V, 5 A, L=5 m one way, round trip, 1.5 mm² copper, n=1 → R=0.11494 Ω, drop=0.5747 V, Vload=11.4253 V, loss=2.8735 W, drop≈4.789167%. Aluminum gives drop≈0.942133 V. Two parallels or one-way calculation halves the corresponding resistance/drop.

References: [NIST, Copper Wire Tables](https://nvlpubs.nist.gov/nistpubs/Legacy/hb/nbshandbook100.pdf), [Trefinasa, Conductor Material Properties](https://www.trefinasa.com/wp-content/uploads/2016/11/overhead_conductors_trefinasa_2016web.pdf).

## 7. ADC scaling

Signal path: measured input → divider → positive gain → ADC-side offset → ADC.

```text
k = Rbottom / (Rtop + Rbottom)
D = 2^N or 2^N−1 (explicit selection)
Vpin = raw Vref / D
Vin = (Vpin − offset)/(k G)
input_volts_per_count = Vref/(D k G)
input_intercept = −offset/(k G)
max_reconstructed_input = (2^N−1) input_volts_per_count + input_intercept
nominal_fullscale_input = (Vref−offset)/(k G)
```

Top resistance may be zero to bypass attenuation. Gain, bottom resistance and reference must be positive. Highest-code reconstruction is deliberately distinguished from the nominal full-scale boundary. Codes at either endpoint trigger a possible clipping warning. Real ADC bin transitions, INL, noise and gain errors are not modeled.

Check: N=12, Vref=3.3 V, raw=2048, Rtop=90 kΩ, Rbottom=10 kΩ, G=2, offset=0.1 V, D=4096 → Vpin=1.65 V, Vin=7.75 V, input LSB=0.0040283203125 V. D=4095 produces Vin≈7.752014652 V.

Firmware constants use 17 significant digits for round-trip double precision, and code bounds are checked in the generated function.

Reference: [TI, How to Convert ADC Code to a Voltage](https://e2e.ti.com/blogs_/archives/b/precisionhub/posts/it-s-in-the-math-how-to-convert-adc-code-to-a-voltage-part-1).

## 8. DAC scaling

```text
D = 2^N or 2^N−1
Vdac = code Vref / D
Vout = G Vdac + offset
step = G Vref / D
required_code = clamp(round((Vdesired−offset)/step), 0, 2^N−1)
achieved = required_code step + offset
error = achieved − Vdesired
max_output = (2^N−1) step + offset
```

Nearest-code rounding uses nonnegative half-up semantics. Clipping is flagged if the desired output lies outside the reachable interval; in that case the error includes saturation, not just quantization. Within range, the ideal nearest-code error is at most half a step. C/C++ conversion handles NaN and clips before integer conversion.

Check: 12 bits, 3.3 V reference, G=2.5, offset=0.25 V, desired=7 V, D=4096 → code=3351, achieved=6.99945068359375 V, error=−0.00054931640625 V, step=0.00201416015625 V.

Denominator selection is device-specific: [Analog Devices AD5696R](https://wiki.analog.com/resources/quick-start/ad5696r) uses 2^N in its transfer equation; [AD5791](https://wiki.analog.com/resources/quick-start/ad5791) provides a 2^N−1 example. Choose the actual datasheet's convention. The app's simple unipolar model is not a full simulation of either device.

## Interpreting status

Green means a finite result without modeled warning conditions. Yellow means review an assumption or design reserve. Red means an entered/model-derived limit is violated. None certifies safety or component suitability. Verify results before use in safety-critical or production hardware.